1. Field of the Invention
The present invention relates to a method and apparatus for reducing gate capacitor stress in an analog circuit, and may be implemented in deep sub-micron CMOS/BiCMOS with a very thin gate oxide layer.
2. Description of the Related Art
Many different analog functions have been implemented in a metal oxide semiconductor field effect transistor (MOSFET) structure through the use of CMOS and BiCMOS technology. Referring to FIGS. 1 and 2, a capacitor 100 (comprising a gate 105 of the FET 200) is one of the passive elements commonly used in analog circuits. FIG. 2 shows a standard illustration of the symbol for a MOSFET, including the gate 105, the source 110, and the drain 115. Often, the size of the capacitors required can be quite large. The resulting MOSFET area required increases proportionally with the capacitance required. For purposes of cost reduction, it is desirable to find ways to reduce the size of MOSFETs used in large capacitors.
As gate length decreases in a deep sub-micron MOSFET device, the gate thickness of the MOSFET also decreases to improve the speed performance of the device. This results in correspondingly lower breakdown voltages for the gate oxide. Many sub-micron CMOS processes offer dual gate oxides to support transistors with two different kinds of operating voltages. For example, see U.S. Pat. Nos. 5,434,531; 5,530,394; 5,744,996; 5,767,733; 5,821,769; and 5,939,934, the contents of each of which are incorporated herein by reference. The lower voltage devices are typically used for implementing high speed/low power digital circuitry, which can easily run at lower voltages. The thicker gate oxide transistors are made available to ease the implementation of analog functions with a certain topology that requires higher voltage operation. In a number of analog functional blocks, fairly large capacitors to ground, or virtual ground, are required. An example is a capacitor used in a gm/C filter, as described in U.S. Pat. No. 5,805,006, the contents of which are incorporated herein by reference. It is possible to implement these capacitors using the thicker gate oxide transistors, which can sustain higher gate breakdown voltage. However, it can be very advantageous to use the thinner gate oxide MOSFETs for the gate capacitor.
Without taking any special precautions, the use of a thinner gate limits the usable gate voltage to the upper voltage limit recommended by the chip manufacturer. In many analog functions, this may not be impractical. For example, it is supposed that in a particular analog gm/C filter implementation, it is desirable to set the common mode output voltage to 1.8 V. Assuming that the process used is a 3.3 V/1.5 V 0.15 xcexcm CMOS process, a thin gate oxide transistor may only work reliably up to 1.5 V of voltage stress. Therefore, assuming that the source 110 and drain 115 are biased at 0 V (as is generally the case, because this ensures that the FET channel is strongly inverted), the 1.8-V common mode voltage is too high for the thin gate oxide grounded capacitor. Using a thicker gate oxide MOSFET would solve this problem because it would safely handle up to 3.3 V of voltage stress. The area of the thick gate oxide used can be more than double the area of a thin gate oxide capacitor.
In view of the foregoing, the present inventors have recognized a need for an implementation of a gate capacitor using a MOSFET having a thin gate oxide and allowing for high values of voltage stress that might otherwise cause the MOSFET to break down.
The present invention is intended to overcome the drawbacks noted above and implements a gate capacitor using a MOSFET having a thin gate oxide layer and allowing for high values of voltage stress that might otherwise cause the MOSFET to break down.
In one aspect, the invention provides a capacitor. The capacitor includes a thin gate oxide layer semiconductor device having a gate oxide layer, means for biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to one of the source and the drain, and means for applying a voltage to a gate of the semiconductor device. The applied gate voltage is greater than a voltage rating of the semiconductor device but less than the sum of the voltage rating and the voltage applied to one of the source and the drain. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.
In another aspect of the invention, a read channel for a hard disk drive includes a thin gate oxide layer semiconductor device having a gate oxide layer, the semiconductor device being used as a gate capacitor. The read channel also includes means for biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to one of the source and the drain, and means for applying a voltage to a gate of the semiconductor device. The applied gate voltage is greater than a voltage rating of the semiconductor device but less than the sum of the voltage rating and the voltage applied to one of the source and the drain. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.
In yet another aspect of the invention, an electrical circuit for amplification of a signal includes a thin gate oxide layer device having a gate oxide layer, the semiconductor device being used as a gate capacitor. The circuit also includes means for biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to one of the source and the drain, and means for applying a voltage to a gate of the semiconductor device. The applied gate voltage is greater than a voltage rating of the semiconductor device but less than the sum of the voltage rating and the voltage applied to one of the source and the drain. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.
In still another aspect of the invention, an apparatus for using a thin gate oxide layer semiconductor device having a gate oxide layer as a gate capacitor includes means for biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to one of the source and the drain, and means for applying a voltage to a gate of the semiconductor device. The voltage applied to the gate is greater than a voltage rating of the semiconductor device but less than the sum of the voltage rating and the voltage applied to one of the source and the drain. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.
In yet another aspect of the invention, an apparatus for preventing voltage breakdown in a thin gate oxide layer semiconductor device being used as a gate capacitor and having a gate oxide layer is provided. The apparatus includes means for applying an input signal having a voltage to a gate of the semiconductor device, means for biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to one of the source and the drain, and means for applying a reference voltage to a substrate to which the semiconductor device is connected. The means for biasing at least one of a source and a drain of the semiconductor device applies a voltage to one of the source and the drain which is less than the sum of the applied reference voltage and a threshold voltage of the semiconductor device, but greater than the difference between the input signal voltage and the voltage rating of the semiconductor device. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.
In still another aspect of the invention, a method of using a thin gate oxide layer semiconductor device having a gate oxide layer as a gate capacitor is provided. The method includes the steps of biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to one of the source and the drain, and applying a voltage to a gate of the semiconductor device. The voltage applied to the gate is greater than a voltage rating of the semiconductor device but less than the sum of the voltage rating and the voltage applied to one of the source and the drain. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.
In yet another aspect of the invention, a method of preventing voltage breakdown in a thin gate oxide layer semiconductor device being used as a gate capacitor and having a gate oxide layer is provided. The method includes the steps of applying an input signal having a maximum voltage to a gate of the semiconductor device, biasing at least one of a source and a drain of the semiconductor device by applying a nonzero voltage to the source and the drain, and applying a reference voltage to a substrate to which the semiconductor device is connected. The bias voltage applied to at least one of the source and the drain is less than the sum of the applied reference voltage and a threshold voltage of the semiconductor device, but greater than the difference between the input signal voltage and the voltage rating of the semiconductor device. The gate of the semiconductor device may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The semiconductor device may be a MOSFET, and it may be manufactured using CMOS technology or BiCMOS technology.